Self-Aligned Crystallographic Multiplication of Nanoscale Silicon Wedges for High-Density Fabrication of 3D Nanodevices

High-density arrays of silicon wedges bound by {111} planes on silicon (100) wafers have been created by combining convex corner lithography on a silicon dioxide hard mask with anisotropic, crystallographic etching in a repetitive, self-aligned multiplication procedure. A mean pitch of around 30 nm has been achieved, based on an initial pitch of ∼120 nm obtained through displacement Talbot lithography. The typical resolution of the convex corner lithography was reduced to the sub-10 nm range by employing an 8 nm silicon dioxide mask layer (measured on the {111} planes). Nanogaps of 6 nm and freestanding silicon dioxide flaps as thin as 1–2 nm can be obtained when etching the silicon at the exposed apices of the wedges. To enable the repetitive procedure, it was necessary to protect the concave corners between the wedges through “concave” corner lithography. The produced high-density arrays of wedges offer a promising template for the fabrication of large arrays of nanodevices in various domains with relevant details in the sub-10 nm range.

The next step was doubling of the periodicity of the V-grooves, i.e. removal of the flat spacers between the 1 st generation V-grooves (see fig. S1 for the general process). This was accomplished with Local Oxidation of Silicon (LOCOS) in combination with a second anisotropic etching, a procedure of which details are described by Wilbers et.al [S5]. In brief, wet oxidation at 800 °C (15 min.; Tempress) yielded a SiO 2 -layer of 7.9 ± 0.4 nm on Si-{111} (i.e. the walls of the V-grooves; for comparison: this oxidation step yields 5.7 ± 0.3 nm SiO 2 on Si-{100}), whereas the Si 3 N 4 -covered (100)-Si surface was only slightly S3 oxidized. A dip in 1% HF (15 sec (at room temperature)) was applied to remove this oxide from the Si 3 N 4 , followed by selective removal of the Si 3 N 4 layer in 85% phosphoric acid (H 3 PO 4 ) (140 °C, 18 min. -BASF). A combination of an UV-ozone treatment (5 min.) and immersion in 1% HF (11 sec. (at room temperature)) was used to remove the interfacial oxide underneath the Si 3 N 4 and resulted in hydrophobic silicon. The exposed Si was etched in 25 wt.% TMAH (70 °C), in which the etch rates of Si-{100} and Si-{111} are ca. 300 nm/min and 9.7 nm/min, respectively. An etch time of 6 min. resulted in a width of ca. 125.0 ± 2.0 nm for both the 1 st and 2 nd generation V-grooves: due to the (slow) etching of Si-{111} the initial width (of ca. 130 nm) of 1 st generation V-grooves is reduced to ca. 125 nm. A 50%-50% duty-cycle of the doubled V-groove pattern -defined as the ratio of the widths of the 1 st and 2 nd generation V-grooves after the KOH and TMAH etching steps -can thus be accomplished via optimization of the etching time in TMAH [30]. After the TMAH etch step the SiO 2 layer was removed with 50% HF (1 min. -BASF).
The periodicity of the realized V-groove pattern was doubled via a combination of SiO 2 -based convex CL and Si 3 N 4 -based concave CL. First, the substrate was wet thermally oxidized for 15 min. at 800 °C (7.9 ± 0.4 nm on Si-{111}). On top of this layer a film of LPCVD Si 3 N 4 was deposited (17 min, 13.1 ± 0.1 nm) onto which corner lithography was applied: the Si 3 N 4 layer was isotropically etched for 18 min. in hot H 3 PO 4 (85%, 140 °C), after which only Si 3 N 4 was left in the concave corners of the V-grooves. Subsequently, convex corner lithography was applied to the SiO 2 layer: isotropic thinning in 1% HF for 67 seconds resulted in exposed Si at the convex corners, whereas the Si-{111}-walls were still covered with SiO 2 and the concave corners with SiO 2 and Si 3 N 4 . With TMAH (25 wt.%, 70 °C) the silicon at the apices was etched for 5.5 min, resulting in a 3 rd generation V-grooves with a width of 61.3 ± 2.0 nm. After cleaning in HNO 3 (fuming 99% and boiling 69%) the remaining layers of SiO 2 and Si 3 N 4 were simultaneously stripped in 50% HF (etch time 2 min. at room temperature).
Finally, a 3 rd doubling of the periodicity of the groove-pattern was realized. The applied procedure was identical to the above-mentioned corner lithography sequence consisting of SiO 2 -convex and Si 3 N 4concave corner processing, with the exception that the etch time in TMAH was 105 seconds. By means of this procedure a 4 th generation V-shaped nano-grooves was created, with a width of 30.6 ± 5.0 nm.
When the above-mentioned V-groove periodicity doubling procedure based on crystallographic nanolithography is combined with standard UV-lithography (Olin 907-17 photoresist) in an orthogonal fashion, i.e. the UV-based mask pattern is 90° rotated with respect to the length-direction of the wedges, it is possible to realize adjacent areas of wedges of which the periodicity varies by a factor 2.

Analysis of the TEM and AFM data obtained of at least one period of the etched silicon nano-wedges
In figure S2 TEM and AFM images are shown of the convex as well as the concave corners of a full nano-wedge period during two key steps shown in fig. 1 of the main text. Fig. S2a1) shows in high detail the grown oxide on the convex and concave corners. The silicon substrate was wet thermally oxidized for 15 min. at 800 °C (7.9 ± 0.4 nm on Si(111), 5.7 ± 0.3 nm on Si (100)). The reason that 2 concave corners are shown is that these corners have a different radius of curvature because of the difference in number of previous oxidation steps. The concave corner on the left is oxidized for the first time, whereas the one on the right is oxidized twice (using the same oxidation settings and an HF strip in between). A first oxidation step with the above-mentioned settings results in a conformal concave oxide thickness (ca. 7.5 nm), whereas the second oxidation is much thinner at the concave corner (ca. 3.9 nm). Fig. S2a2) shows the AFM result of the formed nanowedges.
Figs. S2b1) and b2) correspond to the anisotropic etching step shown in fig. 1c) (main text). In the AFM image clearly the start of the anistropic etching can be identified, beginning exclusively at the convex corner (in 20 wt% KOH at room temperature).   Figure S3. Definition of directions of the stress components developing near the apex of a wedge during thermal oxidation.

3D representation of the double repeated self-aligned multiplying wedge nanomachining procedure
In fig. S4 a 3D representation is given of the (double repeated) self-aligned multiplying wedge nanomachining procedure. At each subfigure a short description of the process step is given. A detailed textual description of the fabrication sequence is provided in SI section 1. Figure S4. 3D representation of the (double repeated) self-aligned multiplying wedge nanomachining procedure.

Uniformity of double repeated self-aligned multiplying wedge nanomachining procedure with tuned 50% duty-cycle
The uniformity of key steps of the self-aligned multiplying wedge nanomachining procedure was first analyzed based on a separate run which includes all steps needed for a single multiplication step (convex corner lithography + anisotropic etching) and which omits the concave (protective corner lithography). On 5x5 locations, distributed across a substrate as indicated in figure S5, SEM images were recorded. Based on these images (a typical example is shown in figure S6), the pitch of the wedges was determined (after 240 sec of TMAH etching). Table S1 shows the obtained pitches at the various locations (coordinates shown in fig. S5); it is noted that the width values in the first column were determined with the software of the SEM, whereas the values in columns 2-4 were obtained by image analysis with CorelDRAW X7. The average (i.e., arithmetic mean) wedge pitch across a substrate is 31.0 nm width a -value (i.e., SD_N) of 1.1 nm. Figure S5. Schematic representation of the 25 locations on 100 mm diameter silicon where SEM images were recorded for uniformity analysis of the wedge nano-machining procedure. S10 Figure S6. SEM image of wedges at location (x,y)=(0,0) (etch time in TMAH 240 s, 70 C, 25 wt.%).  Table S1. Widths of wedges at various locations of a substrate; the coordinates of the locations at which SEM images were taken are shown in fig. S5.

Location Width of wegdes Average
A similar procedure was followed and the TMAH etching step reduced to 60 s . On 5 locations, distributed across a substrate TEM images were recorded, see fig. S7. Based on these 5 images, the spacing between newly formed wedges was determined (after 60 s of TMAH etching). The average (i.e., arithmetic mean) spacing across a substrate is 12.0 nm with a -value (i.e., SD_N) of 0.5 nm. S12 Figure S7. Schematic representation of the 5 locations on 100 mm diameter silicon where TEM images were recorded for uniformity analysis of the wedge nano-machining procedure (after etching in TMAH (70 C, 25 wt.%) for 60 s. The (white) numbers indicate the spacing between newly formed wedges. S13

Typical integration scheme of convex corner lithography for NEMS devices fabrication
Convex corner lithography can be used for fabrication of NEMS devices. For example, high density arrays of nano-cavities can be fabricated (example taken from [S6]), as shown in figure S8. Specific details regarding the realization of nano-cavities: post to silicon nano-wedge templating, a low temperature oxidation step was done (yielding 25 nm SiO 2 at the Si(111) planes). Then a poly-silicon hard mask was deposited that was slightly oxidized and patterned using DTL, 1% HF etching and immersion in 20wt% KOH (room temperature). Subsequently, this poly-silicon mask was used to perform the silicon oxide thinning step (in 1% HF) down to 5 nm. Finally, nano-cavities were etched at the apices in TMAH through the nano-gaps created in the SiO 2 (the gap sizes measured with HR-SEM after cleaving the sample were below 20 nm).